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Very Low Input, MHz Operation, High Efficiency Synchronous Buck
POWER MANAGEMENT Description
The SC4603 is a voltage mode step down (buck) regulator controller that provides accurate high efficiency power conversion from input supply range 2.25V to 5.5V. A high level of integration reduces external component count and makes it suitable for low voltage applications where cost, size and efficiency are critical. The SC4603 drives external complementary power MOSFETs; P-channel on the high side and N-channel on the low side. The use of high side P-channel MOSFETs eliminates the need for an external charge pump and simplifies the high side gate driver. Non-overlap protection is provided for the gate drive signals to prevent shoot through of the MOSFET pair. The voltage drop across the P-channel MOSFET during its conduction is sensed for lossless short circuit current limiting. A low power sleep mode can be achieved by forcing the SYNC/SLEEP pin below 0.8V. A synchronous mode of operation is activated as the SYNC/SLEEP pin is driven by an external clock. The quiescent supply current in sleep mode is typically lower than 10A. A 1.7ms soft start is internally provided to prevent output voltage overshoot during start-up. A 100% maximum duty cycle allows the SC4603 to operate as a low dropout regulator in the event of a low battery condition. The SC4603 is an ideal choice for 3.3V, 5V or other low input supply systems. It's available in 10 pin MSOP package.
SC4603
Features
BICMOS voltage mode PWM controller 2.25V to 5.5V Input voltage range Output voltages as low as 0.5V Sleep mode (Icc = 10A typ) Lossless adjustable overcurrent protection Combination pulse by pulse & hiccup mode current limit High efficiency synchronous switching 0% to 100% Duty cycle range Synchronization to external clock Asynchronous start-up 1MHz frequency of operation 10-Pin MSOP surface mount package
Applications
Distributed power architecture Servers/workstations Local microprocessor core power supplies DSP and I/O power supplies Battery powered applications Telecommunication equipment Data processing applications
Typical Application Circuit
R15 1 RT 34.8k 5 C3 4.7u 1 2 3 C1 R1 20k 150p C2 1n 4 U1 FS VCC SYNC COMP VSENSE ISET PDRV PHASE NDRV GND 6 10 7 9 8 R5 M2 R6 1.0 L1 2.3u C7 150u C4 22u R8 806 C9 1.2n R7 14k R3 C14 33n M1 C10 22u C11 22u
Vin = 2.25V ~ 5.5V
C12 22u C13 22u
Vout = 1.5V (as low as 0.5V * ) /6A
SC4603
1.0
* External components can be modified to provide a Vout as low as 0.5V.
R9 6.98k
Revision: May 5, 2004
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SC4603
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage (VCC) Output Drivers (PDRV, NDRV) Currents Continuous Inputs (VSENSE, COMP, SYNC/SLEEP, FS, ISET) Phase Phase Pulse tpulse < 50ns Operating Ambient Temperature Range Storage Temperature Range Junction Temperature Range Thermal Impedance Junction to Case Thermal Impedance Junction to Ambient Lead Temperature (Soldering) 10 Sec. ESD Rating (Human Body Model)
Symbol
Maximum 6 0.25 6 -0.3 to 5.5 -2 to 6
Units V A V V V C C C C/W C/W C kV
TA TSTG TJ J C J A TLEAD ESD
-40 to +85 -65 to +150 -55 to +150 41.9 113.1 300 2
Electrical Characteristics
Unless otherwise specified, VCC = 3.3V, RT = 21Kohm, TA = -40C to 85C, TA = TJ.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
Parameter Overall Supply Voltage Supply Current, Sleep Supply Current, Operating VCC Turn-on Threshold VCC Turn-off Hysteresis Error Amplifier Internal Reference
Test Conditions
Min
Typ
Max
Unit
2.25 VSYNC/SLEEP = 0V 10 2 2 100
5.5 15 3 2.25
V A mA V mV
VCC = 3.3V, TA = 25C VCC = 3.3V, TA = -40C to 85C
495 492 -0.15 -0.4
500
505 508
mV mV %/V %/V nA dB MHz V/s
Internal Reference Change
VCC = 2.25V to 3.3V, TA = 25C VCC = 3.3V to 5.5V, TA = 25C
0.1 -0.2 200
0.35 0
VSENSE Bias Current Open Loop Gain (1) Unity Gain Bandwidth (1) Slew Rate
(1)
VCOMP = 0.5V to 2.5V
80 (1)
90 8 2.4
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SC4603
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, RT = 21Kohm, TA = -40C to 85C, TA = TJ.
Parameter Error Amplifier (Cont.) VCOMP High VCOMP Low Oscillator Initial Accuracy Voltage Stability Temperature Coefficient Synchronization Frequency SYNC Low Threshold SYNC High Threshold Ramp Peak to Valley (1) Ramp Peak Voltage Ramp Valley Voltage
(1) (1)
Test Conditions
Min
Typ
Max
Unit
ICOMP = -5.5mA ICOMP = 5.5mA
VCC - 0.6
VCC - 0.4 0.35 0.525
V V
TA = 25C, VSYNC/SLEEP = HIGH TA = 25C, VCC = 2.25V to 5.5V TA = -40C to 85C
540
600 1 0.01 1
660
kHz %/V %/C MHz
0.8 2.0 1 1.25 0.25
V V V V V
Sleep, Soft Start, Current Limit Sleep Threshold Measured at VSYNC/SLEEP LOGIC LOW Measured at VSYNC/SLEEP LOGIC HIGH Sleep Input Bias Current (2) Soft Start Time
(1) (2)
0.8 2.0 -50 1.7 -43 -50 +0.3 150 -57
V V nA ms A %/C ns
VSYNC/SLEEP = 0V FSW = 600kHz Bias Current, TJ = 25C Temperature Coefficient
Current Limit Threshold
Current Limit Blank Time(1) N-Channel and P-Channel Driver Outputs Pull Up Resistance (PDRV) (2) Pull Down Resistance (PDRV) (2) Pull Up Resistance (NDRV) (1) Pull Down Resistance (NDRV) (2) PDRV Output Rise Time PDRV Output Fall Time
(2)
Vcc = 3.3V, IOUT = -100mA (source) Vcc = 3.3V, IOUT = 100mA (sink) Vcc = 3.3V, IOUT = -100mA (source) Vcc = 3.3V, IOUT = 100mA (sink) Vgs = 3.3V, COUT = 1.0nF Vgs = 3.3V, COUT = 1.0nF
3.4 3 3.4 1.5 8 7
ohms ohms ohms ohms ns ns
(2)
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SC4603
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, RT = 21Kohm, TA = -40C to 85C, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
N-channel and P-Channel Driver Outputs (Cont.) NDRV Output Rise Time NDRV Output Fall Time
(1)
Vgs = 3.3V, CCOMP = 1nF Vgs = 3.3V, CCOMP = 1nF
8 3 adaptive 30 50
ns ns
(2)
Deadtime Delay (PDRV high to NDRV high) (3) Deadtime Delay (NDRV low to PDRV low) (1)
ns
Notes: (1). Guaranteed by design. (2). Guaranteed by characterization. (3). Dead time delay from PDRV high to NDRV high is adaptive. As the phase node voltage drops below 600mV due to PDRV high, NDRV will start to turn high.
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SC4603
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number(1) SC4603IMSTRT(2) Device MSOP-10
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. (10 Pin MSOP)
Pin Descriptions
VCC: Positive supply rail for the IC. Bypass this pin to GND with a 0.1 to 4.7F low ESL/ESR ceramic capacitor. GND: All voltages are measured with respect to this pin. All bypass and timing capacitors connected to GND should have leads as short and direct as possible. FS: An external resistor connected with FS pin sets the clock frequency. SYNC/SLEEP: The oscillator frequency of SC4603 is set by FS when SYNC/SLEEP is pulled and held above 2V. Its synchronous mode operation is activated as the SYNC/SLEEP is driven by an external clock. The oscillator and PWM are designed to provide practical operation to 1MHz when synchronized. Sleep mode is invoked if SYNC/SLEEP is pulled and held below 0.8V which can be accomplished by an external gate or transistor. The Sleepmode supply current is 10A typical. VSENSE: This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the Buck converter. It senses the output voltage through an external divider. COMP: This is the output of the voltage amplifier. The voltage at this output is connected to the inverting input of the PWM comparator. A lead-lag network around the voltage amplifier compensates for the two pole LC filter characteristic inherent to voltage mode control and is required in order to optimize the dynamic performance of the voltage mode control loop. PHASE, ISET: PHASE input is connected to the junction between the two external power MOSFET transistors. The voltage drop across the upper P-channel device is monitored by PHASE and ISET during PFET conduction and forms the current limit comparator and logic that sets the PWM latch and terminates the PFET output pulse once excessive voltage drop across the PFET is detected. The controller stops switching and goes through a soft start sequence once the converter output voltage drops below 70% its nominal voltage. This prevents excess power dissipation in the PMOSFET during a short circuit. The current limit threshold is set by the external resistor between VCC and ISET. The internal 50A current source has a positive temperature coefficient that can compensate PMOSFET Rdson variation due to its junction temperature change. PDRV, NDRV: The PWM circuitry provides complementary drive signals to the output stages. The Cross conduction of the external MOSFETs is prevented by monitoring the voltage on the P-channel and N-channel driver pins in conjunction with a time delay optimized for FET turn-off characteristics.
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SC4603
POWER MANAGEMENT Typical Characteristics
Oscillator Internal Accuracy vs Input Voltage
Internal Accuracy (kHz)
Oscillator Internal Accuracy vs Temperature
602.0 600.0 598.0 596.0 594.0 592.0 -40 -20 0 20 40 60 80 Temperature (C)
Vcc = 3.3V
600
Internal Accuracy (kHz)
595 590 585 580 2 2.5 3 3.5
Vcc (V) TA = 25C
4
4.5
5
5.5
Sense Voltage vs Input Voltage
501.0 500.5 500.0 499.5 499.0 498.5 498.0 497.5 2
Sense Voltage (mV)
Sense Voltage vs Temperature
501.0 500.5 500.0 499.5 499.0 498.5 -40 -20 0 20 40 60 80
Temperature (C)
Vcc = 3.3V
Sense Voltage (mV)
TA = 25C
2.5
3
3.5
Vcc (V)
4
4.5
5
5.5
Current Limit Bias Current vs Input Voltage
Current Limit Bias Current (uA)
Current Limit Bias Current vs Temperature
60 58 56 54 52 50 48 46 44 42 40 38
Vcc = 3.3V
53 52 52 51 51 50 2 2.5 3 3.5
Vcc (V) Current Limit Bias Current (uA)
TA = 25C
4
4.5
5
5.5
-40
-20
0
20
40
60
80
Temperature (C)
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SC4603
POWER MANAGEMENT Block Diagram
Applications Information
Enable Pulling and holding the SYNC/SLEEP pin below 0.8V initializes the SLEEP mode of the SC4603 with its typical SLEEP mode supply current of 10uA. During the SLEEP mode, the high side and low side MOSFETs are turned off and the internal soft start voltage is held low. Oscillator The oscillator uses an external resistor to set the oscillation frequency when the SYNC/SLEEP pin is pulled and held above 2V. The ramp waveform is a triangle at the PWM frequency with a peak voltage of 1.25V and a valley voltage of 0.25V. A 100% maximum duty cycle allows the SC4603 to operate as a low dropout regulator in the event of a low battery condition. The resistor tolerance adds to the accuracy of the oscillator frequency. The external resistor connected to the FS pin, as shown below determines the approximate operating frequency:
fS = 126 * 10 8 RT
An external clock connected to the SYNC/SLEEP activates its synchronous mode and the frequency of the clock can be up to 1MHz. UVLO When the SYNC/SLEEP pin is pulled and held above 2V, the voltage on the VCC pin determines the operation of the SC4603. As VCC increases during start up, the UVLO block senses VCC and keeps the high side and low side MOSFETs off and the internal soft start voltage low until VCC reaches 2.25V. If no faults are present, the SC4603 will initiate a soft start when VCC exceeds 2.25V. A hysteresis (100mV) in the UVLO comparator provides noise immunity during its start up.
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SC4603
POWER MANAGEMENT Applications Information - (Cont.)
Soft Start The soft start function is required for step down controllers to prevent excess inrush current through the DC bus during start up. Generally this can be done by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up the error amp reference. The closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. With this, the inrush current from the input side is controlled. The duration of the soft start in the SC4603 is controlled by an internal timing circuit which is used during start up and over current to set the hiccup time. The soft start time can be calculated by:
TSOFT _ START = 1020 fS
IMAX and the internal 50A pull down current available on the ISET pin based on the following expression:
R SET = IMAX * RDS( ON) 50A
Kelvin sensing connections should be used at the drain and source of P-MOSFET. The RDS(ON) sensing used in the SC4603 has an additional feature that enhances the performance of the over current protection. Because the RDS(ON) has a positive temperature coefficient, the 50A current source has a positive coefficient of about 0.3%/C providing first order correction for current sensing vs temperature. This compensation depends on the high amount of thermal transferring that typically exists between the high side PMOSFET and the SC4603 due to the compact layout of the power supply. When the converter detects an over current condition (I > IMAX) as shown in Figure 1, the first action the SC4603 takes is to enter cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases. Then the output voltage is monitored. If the over current and low output voltage (set at 70% of nominal output voltage) occur at the same time, the Hiccup mode operation (Point C to Point D) of the SC4603 is invoked and the internal soft start capacitor is discharged. This is like a typical soft start cycle.
As can be seen here, the soft start time is switching frequency dependant. For example, if f s = 600kHz, T SOFT_ START = 1020/600k = 1.7ms. But if f s = 1MHz, TSOFT_START = 1020/1M = 1.02ms. The SC4603 implements its soft start by ramping up the error amplifier reference voltage providing a controlled slew rate of the output voltage, then preventing over. shoot and limiting inrush current during its start up. Over Current Protection Over current protection for the SC4603 is implemented by detecting the voltage drop of the high side P-MOSFET during conduction, also known as high side RDS(ON) detection. This loss-less detection eliminates the sense resistor and its loss. The overall efficiency is improved and the number of components and cost of the converter are reduced. RDS(ON) sensing is by default inaccurate and is mainly used to protect the power supply during a fault case. The over current trigger point will vary from unit to unit as the RDS(ON) of P-MOSFET varies. Even for the same unit, the over current trigger point will vary as the junction temperature of P-MOSFET varies. The SC4603 provides a built-in 50A current source, which is combined with RSET (connected between VCC and ISET) to determine the current limit threshold. The value of RSET can be properly selected according to the desired current limit point
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A
VO - nom
B
0.6875 VO - nom 0.7
C
VO
D
IMA IO
Figure 1. Over current protection characteristic of SC4603
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SC4603
POWER MANAGEMENT Applications Information - (Cont.)
Power MOSFET Drivers The SC4603 has two drivers for external complementary power MOSFETs. The driver block consists of one high side P-MOSFET driver, PDRV, and one low side NMOSFET driver, NDRV, which are optimized for driving external power MOSFETs in a synchronous buck converter. The output drivers also have gate drive non-overlap mechanism that gives a dead time between PDRV and NDRV transitions to avoid potential shoot through problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, a 6A converter can be achieved. As shown in Figure 2, td1, the delay from the P-MOSFET off to the N-MOSFET on is adaptive by detecting the voltage of the phase node. td2, the delay from the N-MOSFET off to the P-MOSFET on is fixed, is 50ns for the SC4603. This control scheme guarantees avoiding the cross conduction or shoot through between two MOSFETs and minimizes the conduction loss in the bottom diode for high efficiency applications.
PMOSFET Gate Drive NMOSFET Gate Drive
ripple current to be within 15% to 30% of the maximum output current. The inductor value can be determined according to its operating point and the switching frequency as follows:
L= Vout ( Vin - Vout ) Vin fs I IOMAX
Where: fs = switching frequency and I = ratio of the peak to peak inductor current to the maximum output load current. The peak to peak inductor current is:
Ip -p = I * IOMAX
After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation.
IPEAK = IOMAX + Ip -p 2
Phase node
Ground
td1
td2
The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce inductor's copper loss. The core loss can be found in the manufacturer's datasheet. The inductor's copper loss can be estimated as follows:
PCOPPER = I2LRMS R WINDING
Figure 2. Timing Waveforms for Gate Drives and Phase Node
Inductor Selection The factors for selecting the inductor include its cost, efficiency, size and EMI. For a typical SC4603 application, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the inductor value will decrease the ripple level of the output voltage while the output transient response will be degraded. Low value inductors offer small size and fast transient responses while they cause large ripple currents, poor efficiencies and more output capacitance to smooth out the large ripple currents. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. A good tradeoff among its size, loss and cost is to set the inductor
Where: ILRMS is the RMS current in the inductor. This current can be calculated as follows:
ILRMS = IOMAX 1 + 1 I2 3
Output Capacitor Selection Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the SC4603 regulates the inductor current to a new value
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SC4603
POWER MANAGEMENT Applications Information - (Cont.)
during a load transient, the output capacitor delivers all the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Surface mount speciality polymer aluminum electrolytic chip capacitors in UE series from Panasonic provide low ESR and reduce the total capacitance required for a fast transient response. POSCAP from Sanyo is a solid electrolytic chip capacitor which has a low ESR and good performance for high frequency with a low profile and high capacitance. Above mentioned capacitors are recommended to use in SC4603 applications. Input Capacitor Selection The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction mode, the RMS value of the input capacitor can be calculated from:
ICIN(RMS ) Vout ( Vin - Vout ) = IOMAX 2 Vin
Because the input capacitor is exposed to the large surge current, attention is needed for the input capacitor. If tantalum capacitors are used at the input side of the converter, one needs to ensure that the RMS and surge ratings are not exceeded. For generic tantalum capacitors, it is wise to derate their voltage ratings at a ratio of 2 to protect these input capacitors. Power MOSFET Selection The SC4603 can drive a P-MOSFET at the high side and an N-MOSFET synchronous rectifier at the low side. The use of the high side P-MOSFET eliminates the need for an external charge pump and simplifies the high side gate driver circuit. For the top MOSFET, its total power loss includes its conduction loss, switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bottom diode, shown as follows:
PTOP _ TOTAL = I2 TOP _ RMS R TOP _ ON + ITOP _ PEAK VI fs VGATE RG
(Q GD + Q GS 2 ) + Q GT VGATE fs + (Q OSS + Q rr ) VI fs
This current gives the capacitor's power loss as follows:
PCIN = I2 CIN(RMS ) R CIN(ESR )
This capacitor's RMS loss can be a significant part of the total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor's ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by:
CIN = IOMAX D (1 - D) fs ( VI - IOMAX R CIN(ESR ) )
Where: RG = gate drive resistor, QGD = the gate to drain charge of the top MOSFET, QGS2 = the gate to source charge of the top MOSFET, QGT = the total gate charge of the top MOSFET, QOSS = the output charge of the top MOSFET, and Qrr = the reverse recovery charge of the bottom diode. For the top MOSFET, it experiences high current and high voltage overlap during each on/off transition. But for the bottom MOSFET, its switching voltage is the bottom diode's forward drop during its on/off transition. So the switching loss for the bottom MOSFET is negligible. Its total power loss can be determined by:
PBOT _ TOTAL = I2 BOT _ RMS R BOT _ ON + Q GB VGATE fs + ID _ AVG VF
Where: D = VO/VI , duty ratio and VI = the given input voltage ripple.
Where: QGB = the total gate charge of the bottom MOSFET and VF = the forward voltage drop of the bottom diode.
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SC4603
POWER MANAGEMENT Applications Information - (Cont.)
For a low voltage and high output current application such as the 3.3V/1.5V@6A case, the conduction loss is often dominant and selecting low RDS(ON) MOSFETs will noticeably improve the efficiency of the converter even though they give higher switching losses. The gate charge loss portion of the top/bottom MOSFET's total power loss is derived from the SC4603. This gate charge loss is based on certain operating conditions (fs, VGATE, and IO). The thermal estimations have to be done for both MOSFETs to make sure that their junction temperatures do not exceed their thermal ratings according to their total power losses PTOTAL, ambient temperature TA and their thermal resistances R JA as follows:
C1 R1
For example, if
VREF @ 2.25 V =
VCC = 2.25 V,
the reference voltage,
V
REF
@ 3.3V
+
Vref @ 3.3 V * 100
Internal Reference
Change @ 2.25V * VCC - 3.3V =
500 + 500 * 0.1 * 2.25 - 3.3 = 500.5(mV ) 100
5 1 2 3 4 C2 FS VCC SYNC COMP VSENSE ISET PDRV PHASE NDRV GND 6 10 7 9 8 C9 C4 R L1
Vout
SC4603
R8
R7
TJ(max)
P < TA + TOTAL R JA
R9
Loop Compensation Design: For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. The SC4603 has an internal error amplifier and requires the compensation network to connect among the COMP pin and VSENSE pin, GND, and the output as shown in Figure 3. The compensation network includes C1, C2, R1, R7, R8 and C9. R9 is used to program the output voltage according to:
VOUT = 0.5 (1 + R7 ) R9
Figure 3. Compensation network provides 3 poles and 2 zeros. For voltage mode step down applications as shown in Figure 3, the power stage transfer function is:
1+ G VD (s) = VIN s 1 RC C4
1+ s
L1 + s 2L1C 4 R
Where: R = load resistance and RC = C4's ESR. The compensation network will have the characteristic as follows:
s s 1+ Z1 Z 2 GCOMP (s) = I s s s 1+ 1+ P1 P 2 1+
As indicated in Internal Reference Change section, the internal reference voltage (measured at VSENSE pin) changes slightly if the input voltage of the SC4603 is away from 3.3V.
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SC4603
POWER MANAGEMENT Applications Information - (Cont.)
Where
I = 1 R 7 ( C1 + C 2 ) 1 = R1 C 2
The compensated loop gain will be as given in Figure 4:
T Z1 o Z2 Loop gain T(s) -20dB/dec c p1 p2 Power stage GVD(s) ESR -40dB/dec
Z1 Z 2 = P1
Gd 0dB
1 (R 7 + R 8 ) C 9 C1 + C 2 = R 1 C1 C 2 1 R 8 C9
P 2 =
After the compensation, the converter will have the following loop gain:
T(s) = GPWM GCOMP (s) GVD (s) = s 1 s s 1 1+ I VIN 1 + VM RC C4 Z1 Z 2 s s L s 1+ 1+ 1 + s + s2LC P1 P 2 R 1+
Figure 4. Asymptotic diagrams of power stage and its loop gain. Layout Guidelines In order to achieve optimal electrical, thermal and noise performance for high frequency converters, special attention must be paid to the PCB layouts. The goal of layout optimization is to identify the high di/dt loops and minimize them. The following guideline should be used to ensure proper functions of the converters. 1. A ground plane is recommended to minimize noises and copper losses, and maximize heat dissipation. 2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if possible. 3. The VCC bypass capacitor should be placed next to the VCC and GND pins. 4. The trace connecting the feedback resistors to the output should be short, direct and far away from the noise sources such as switching node and switching components. 5. Minimize the traces between PDRV/NDRV and the gates of the MOSFETs to reduce their impedance to drive the MOSFETs. 6. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. 7. ISET and PHASE connections to P-MOSFET for current sensing must use Kelvin connections.
Where: GPWM = PWM gain and VM = 1.0V, ramp peak to valley voltage of SC4603. The design guidelines for the SC4603 applications are as following: 1. Set the loop gain crossover corner frequency C for given switching corner frequency S =2 fs, 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select Z1 and Z2 such that they are placed near O to damp the peaking and the loop gain has a -20dB/dec rate to go across the 0dB line for obtaining a wide bandwidth. 4. Cancel the zero from C4's ESR by a compensator pole P1 (P1 = ESR = 1/( RCC4)), 5. Place a high frequency compensator pole p2 (p2 = pfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at C.
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SC4603
POWER MANAGEMENT Applications Information - (Cont.)
Layout Guidelines (Cont.) 8. Maximize the trace width of the loop connecting the inductor, bottom MOSFET and the output capacitors. 9. Connect the ground of the feedback divider and the compensation components directly to the GND pin of the SC4603 by using a separate ground trace. Then connect this pin to the ground of the output capacitor as close as possible. Design Example 1: 3.3V to 1.5V @ 5A application with SC4603 (NH020 footprint).
R15 1 R3 U1 5 C3 4.7u R2 3.32k C1 R1 20k 150p C2 820p 1 2 3 4 FS VCC ISET PDRV 6 10 7 9 8 R5 M2 R6 1.0 L1 1.1u C14 33n C10 22u C11 22u
Vin = 3.3V
M1
RT 21k
SY NC/SLEEPPHASE COMP VSENSE NDRV GND
Vo = 1.5V/5A
C7 150u C4 22u R8 604 C9 820p R7 13k
SC4603
1.0
R9 6.49k
Figure 5. Schematic for 3.3V/1.5V @ 5A application
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SC4603
POWER MANAGEMENT Bill of Materials - 3.3V to 1.5V @ 5A
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Qty 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 1 1 1 1 C1 C2 C3 C7 C9 C10,C11,C4 C 14 L1 M1 M2 RT R1 R2 R7 R8 R5,R6 R15 R3 R9 U1 Reference 150pF 820pF 4.7uF 150uF 820pF 22uF, 1210 33nF 1.1uH MOSFET P, S0-8 MOSFET N, S0-8 21k 20k 3.32k 13k 604 1 1 2.94k 6.49k S C 4603 Semtech P/N: SC4603IMSTRT Fairchild P/N: FDS 6375 Fairchild P/N: FDS 6680A TDK P/N: C3225X5R0J226M Panasonic. P/N: 6.3V, SP Value Part No./Manufacturer
Key components: U1: SC4603, Semtech M1: FDS 6375, SO-8, Fairchild M2: FDS 6680A, SO-8, Fairchild L1: SMT power inductor, 1.1uH ETQP6F1R1H, Panasonic. Unless specified, all resistors and capacitors are in SMD 0603 package. Resistors are +/-1% and all capacitors are +/-20%
2004 Semtech Corp.
14
www.semtech.com
SC4603
POWER MANAGEMENT PCB Layout - 3.3V to 1.5V @ 6A
Top
Bottom
Top
Bottom
2004 Semtech Corp.
15
www.semtech.com
SC4603
POWER MANAGEMENT Outline Drawing - MSOP-10
Land Pattern - MSOP-10
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp.
16
www.semtech.com

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